Challenges in the Design of Security-Aware Processors

Secure information processing increases in importance as more of our daily transactions are carried out in cyberspace. Cyber security provides assurances and safeguards necessary for the smooth functioning of cyber space interactions and services. Such interactions and services are built upon hardware and software technology for computing, communications and storage. Yet hardware and software technology has not had secure or trustworthy operations as a fundamental design goal. Rather, the increase in transistors in chips, and our educational and research efforts, have been directed mainly towards improving performance, cost and power in hardware, and improving functionality, versatility and ease-of-use in software. Approaches to cyber security have focused on reactive measures, perimeter security and software implementations. In contrast, we propose a proactive approach to cyber security, where every component, hardware, software or networking, has secure or trustworthy operation as a primary design goal. Architecture for cyber security must be defined at many levels. At the foundational level, if we want core hardware and software to be more responsible for cyber security, what architectural features must be included? How do we translate business and personal security needs, in addition to military and national security needs, into scalable technology features? In this talk, we focus on processors as the engines of the Information Age upon which all software runs. What does it mean for a processor to be security-aware? We illustrate with a few examples. In the area of e-commerce and e-business, we discuss how the processor can make cyber transactions more trustworthy. Can cryptography algorithms, and security protocols, be radically accelerated to provide needed confidentiality, data integrity, digital signatures and user authentication, in an automatic and painless way? In the area of service availability, we discuss whether the processor can provide defenses against misuse of computers by malicious third parties. Are there ways processor architecture can be enhanced to detect, prevent or mitigate potentially disastrous Distributed Denial of Service attacks? What are the processor and software vendors’ responsibilities in providing best-effort security features? What are the technical, policy and social challenges in digital rights management (DRM) with regard to built-in anti-piracy mechanisms? Many of these issues have legal, economic, social and ethical aspects, in addition to technological possibilities and limitations. We propose that it is time to consider how technology in general, and processor architecture in particular, can be designed to facilitate greater security and trust in cyberspace transactions and services.